1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a data interface circuit, a nonvolatile memory device including the same and operating method thereof.
2. Description of the Related Art
In general, semiconductor memory devices are classified as a volatile memory device or a nonvolatile memory device according to whether or not data are preserved when a power supply is cut off. The nonvolatile memory device may have both advantages of a random access memory (RAM), which can freely record and erase data, and advantages of a read only memory (ROM), which can retain stored data without supply of power. In particular, because the degree of integration of a nonvolatile memory device, such as a flash memory, is relatively easier to increase, nonvolatile memory devices have recently been adopted to various fields requiring storage of mass data.
In a conventional nonvolatile memory device, because it takes a significant amount of time to write data to a memory cell or read the written data, a single data rate (SDR) mechanism for inputting/outputting data in synchronization with a rising edge or a falling edge of a clock signal is not given much weight in a total performance of the memory device. However, as a speed for reading/writing data increases, e.g., a size of a page buffer increases up to 8K Byte from 1K Byte, the total performance of the memory device depends more heavily upon the SDR mechanism. To improve the total performance of the memory device, a double data rate (DDR) for inputting/outputting data in synchronization with both a rising edge and a falling edge of a clock signal has been introduced.
FIG. 1 is a block diagram showing a configuration of a conventional nonvolatile memory device.
Referring to FIG. 1, the conventional nonvolatile memory device comprises a memory cell array 101, a page buffer unit 103, a column decoder 105, an address counter 107, a row decoder 109, and a control logic 111.
Hereafter, a program operation for storing data in the conventional nonvolatile memory device will be illustrated.
First, a command CMD, a row address RA, and a start column address CA are inputted to the nonvolatile memory device through input/output (I/O) lines (not shown). Here, the start column address CA is a column address when data are inputted at a first time. Since the nonvolatile memory device generally receives and outputs data on a page-by-page basis, addresses may be generated by sequentially increasing the start column address CA after the start column address CA is inputted, and then the generated addresses may be allocated to consecutive input data.
The row decoder 109 receives the row address RA and activates one of a plurality of word lines WL, which corresponds to the row address RA. The address counter 107 generates a count column address CA_CNT by sequentially increasing the start column address CA. The column decoder 105 loads input data DIN on the page buffer unit 103 through a plurality of data lines DL corresponding to the count column address CA_CNT. The loaded input data DIN is transferred to one of a plurality of bit lines BL, which corresponds to the count column address CA_CNT, so as to be stored in a memory cell among the memory cell array 101, which is selected by the activated word line WL and the bit line BL corresponding to the count column address CA_CNT. The control logic 111 receives the command CMD to control operations of components such as the page buffer unit 103, the column decoder 105, the address counter 107, and the row decoder 109.
FIG. 2 is a timing diagram depicting a data input operation of the conventional nonvolatile memory device shown in FIG. 1 according to a DDR method.
Referring to FIG. 2, the nonvolatile memory device according to the DDR method receives input data DIN in synchronization with rising and falling edges of an internal clock CLK. That is, the data input operation according to the DDR method is performed in pairs at each rising and falling edge of the internal clock CLK. Accordingly, the input data DIN inputted to the nonvolatile memory device are classified into rising data D0, D2, D4, . . . , which are inputted in synchronization with the rising edge of the internal clock CLK, and falling data D1, D3, D5, . . . , which are inputted in synchronization with the falling edge of the internal clock CLK. The nonvolatile memory device according to the DDR method may perform the data input operation at a high speed by inputting the above rising and falling data in different data lines. In detail, the rising data are transferred to an even data line DL_EV while the falling data are transferred to an odd data line DL_OD.
Furthermore, since a pair of the rising and falling data is processed during one period of the internal clock CLK, a column address is classified into an even column address and an odd column address. That is, a pair of the even and odd column addresses is generated during one period of the internal clock CLK. At this time, the address counter 107 generates the count column address CA_CNT by sequentially increasing the start column address CA by 2 whenever the internal clock CLK is toggled. Accordingly, the even column address is allocated to the rising data D0, D2, D4, . . . , and the odd column address is allocated to the falling data D1, D3, D5, . . . .
Meanwhile, the conventional nonvolatile memory device according to the DDR method may allocate an even column address to a first data, which is inputted at the first time, and transfers the first data to an even data line. Then, the conventional nonvolatile memory device may allocate an odd column address to a second data, which is inputted subsequent to the first data, and transfers the second data to an odd data line. That is, since the even column address may be fixed to be allocated to the first data which is inputted at the first time, the conventional nonvolatile memory device may have difficulty randomly inputting/outputting the data.